Midstall Software
Open Source FPGA
Aegis
Open Source FPGA Architecture
A fully open source FPGA architecture targeting proven silicon processes. Aegis provides a complete, reproducible toolchain from HDL to bitstream.
View on GitHubOPEN SOURCE FPGA
AEGISTERRA-1
The flagship Aegis device, targeting the SkyWater 130nm process node. Designed for general-purpose FPGA applications with a focus on openness and reproducibility.
A
PROCESS
130nm
LUT4
~2880
BRAM
128
DSP18
64
I/O PADS
224
SERDES
4
CLOCK
2 (8 out)
ROUTING
4/edge
GRID
48x64
OPEN SOURCE FPGA
AEGISLUNA-1
Compact FPGA device targeting the GlobalFoundries 180nm process node. Optimized for smaller, cost-effective designs.
PROCESS
180nm
LUT4
~760
BRAM
40
DSP18
40
I/O PADS
118
SERDES
1
CLOCK
1 (4 out)
ROUTING
1/edge
GRID
19x40