Secure Enclave for RISC-V
Albion
Secure Enclave Architecture
A confidential-computing and secure-control architecture for RISC-V SoCs. Albion provides hardware-rooted security with a Secure Execution Processor (SEP) as the foundation of trust.
Coming SoonKey Features
Secure Execution Processor
Dedicated SEP built on a custom core designed for security and deterministic operations, serving as the hardware root of trust and treating the Application Processor as untrusted by default.
Memory Protection
Full memory monitoring with immutable regions and access-restricted pages to guard against Row Hammer and other attacks.
Integrated TPM 2.0
Built-in TPM 2.0 support with the ability to interface with external TPMs for platform integrity.
Confidential Computing
Hardware-enforced confidential computing via hypervisor extension for secure workload isolation.
Instruction Monitoring
Decode-stage instruction monitoring for real-time security enforcement at the hardware level.
Secure Boot
Staged and secure boot flow ensuring platform integrity from power-on through application launch.